The present invention relates to fabricating self-aligned metal oxide semiconductor field effect transistors (MOSFETS), and more particularly, to fabricating self-aligned, inversion mode gallium arsenide MOSFETS with excellent electrical characteristics.
The difficulty of increasing performance in sub-100 nm silicon (Si) complementary metal-oxide semiconductor (CMOS) technology has renewed interest in the use of Group III-V channel materials for advanced very large-scale integration (VLSI) CMOS. Gallium Arsenide (GaAs) is an attractive choice due to its relative maturity compared to other Group III-V compounds, its high electron mobility (˜6× compared to Si), and its lattice matching with germanium (Ge). The main barrier towards implementing enhancement- or depletion-mode GaAs MOSFETs for VLSI application is the difficulty of forming a high-quality gate insulator that passivates the interface states and prevents Fermi level pinning at the GaAs surface. However, other problems also need to be overcome including poor thermal stability of the gate stack and the lack of a self-aligned contacting scheme.
Recently, GaAs n-channel metal-oxide semiconductor (NMOS) capacitors with an in-situ molecular beam epitaxy (MBE) grown amorphous silicon (α-Si) passivation layer and ex-situ physical vapor deposition (PVD) hafnium oxide (HfO2) gate dielectric have shown excellent electrical characteristics. Interface state densities Dit as low as 1×1011/cm2.eV are obtained with excellent thermal stability of the GaAs/α-Si/SiO2/HfO2. When self-aligned GaAs MOSFETs were fabricated using conventional metal-oxide semiconductor (MOS) processes, the devices exhibited poor electrical characteristics, namely large subthreshold slope and small on-off current ratio of 103, a value that was limited by gate leakage current. The poor electrical characteristics and high gate leakage were attributed to GaAs/α-Si/SiO2/HfO2 interface degradation caused by conventional high-temperature front end of the line MOS processes.
Therefore, there is a need for a method of fabricating a self-aligning, inversion mode GaAs MOSFET with excellent electrical characteristics.